1. Technical Field
The present invention relates to a flip chip mounting process for mounting a semiconductor chip over a wiring substrate, and a flip chip assembly. In particular, the present invention relates to a flip chip mounting process that are high in productivity and can be applicable to a fine-pitch semiconductor chip, and also it relates to a flip chip assembly.
2. Description of the Related Art
With a development of high density and high integration of a semiconductor integrated circuit (LSI) used for electronics device, higher pin count and finer pitch of electrode terminals of LSI chip have been rapidly developed in recent years. The LSI chip is mounted over a wiring substrate by generally employing a flip chip mounting process in order to decrease wiring delay. It is common practice in this flip chip mounting process to form solder bumps on the electrode terminals of the LSI chip, and then connect, through such solder bumps, all the electrode terminals to all electrodes formed on the wiring substrate in a batch process.
For mounting a next-generation LSI having 5000 or more electrode terminals over the wiring substrate, it is required to form fine-pitch bumps with its pitch of 100 μm or less. It is, however, difficult for a conventional solder bump forming process to form such fine-pitch bumps. Moreover, from a viewpoint that a large number of bumps must be formed according to the number of the electrode terminals, a high productivity is required for reducing a manufacturing cost by reducing mounting tact time per chip.
Conventionally, there has been developed a plating process and a screen printing process as a bump forming process. The plating process is convenient for achieving the fine pitch, but it is complicated and compromises the productivity. The screen printing process, on the other hand, has a high productivity, but is not convenient for achieving the fine pitch because a mask is used.
Recently, there has been developed several processes for selectively forming solder bumps on electrodes of a LSI chip or wiring substrate. These processes are not only convenient for forming fine bumps, but also convenient for achieving a high productivity since a plurality of the fine bumps can be formed in a batch process. Accordingly they are expected as promising processes that can be applicable to the mounting of the next-generation LSI over the wiring substrate.
According to one of these promising processes, a solder paste comprising a mixture of solder powder and a flux is applied directly onto a substrate having electrodes thereon, and subsequently the substrate is heated so as to melt the solder powder and then form the bumps selectively on the electrodes having high wettability without causing an electrical short circuit between the adjacent electrodes. See Japanese Patent Kokai Publication No. 2000-94179 (which is hereinafter referred to also as “Patent literature 1”), for example.
There is also another process wherein a paste composition (so-called “deposition type solder using chemical reaction”) mainly comprising organic acid lead salt and tin metal is applied directly onto a substrate, and subsequently the substrate is heated so as to induce a displacement reaction for Pb and Sn, and thereby Pb/Sn alloy is selectively deposited on electrodes of the substrate. See Japanese Patent Kokai Publication No. H01-157796 (which is hereinafter referred to also as “Patent literature 2”) and “Electronics Packaging Technology”, issued on September, 2000, pp. 38-45 (which is hereinafter referred to also as “Non-patent literature 1”), for example.
A bump forming process disclosed in Patent literature 1 is specifically designed for preventing a shirt circuit between the adjacent electrodes as well as providing solder powder with wettability to metal by controlling surface oxidation of the solder powder. However, the controlling of an extent and a process of the oxidation is not necessarily enough for satisfying both of “providing of wettability” and “prevention of shirt circuit” that are inherently conflicting requirements. Moreover, in the case of the deposition type solder material disclosed in Patent literature 2, the material takes advantage of a particular chemical reaction, and thus it has low flexibility in a selection of solder composition, making it difficult to use Pb-free solder.
By the way, in a flip chip mounting process employing a conventional bump forming technique, subsequent to mounting a semiconductor chip over a wiring substrate having bumps formed thereon, it is additionally required that a resin (which is called “underfill”) is poured into a clearance gap formed between the wiring substrate and the semiconductor chip so as to secure the semiconductor chip to the wiring substrate.
Therefore, there has been developed a flip chip mounting process using anisotropic conductive material wherein opposing electrode terminals of a semiconductor chip and a wiring substrate are electrically connected to each other, and at the same time the semiconductor chip is secured to the wiring substrate. See Japanese Patent Kokai Publication No. 2000-332055 (which is hereinafter referred to also as “Patent literature 3”), for example. In this process, a thermosetting resin comprising electrically conductive particles is supplied between the wiring substrate and the semiconductor chip, and subsequently the semiconductor chip is pressed and at the same time the thermosetting resin is heated. As a result, the electrical connection between the electrode terminals of the semiconductor chip and the wiring substrate, and the securing of the semiconductor chip to the wiring substrate are concurrently achieved.
Furthermore, there is a proposed process for mounting a semiconductor chip over a substrate wherein a resin comprising low-melting-point metal filler (i.e., electrically conductive particles) is used. See Japanese Patent Kokai Publication No. 2004-260131 (which is hereinafter referred to also as “Patent literature 4”), Non-patent literature 1 and “Technical Report of IEICE, EMD96-15” (which is hereinafter referred to also as “Non-patent literature 2”), for example.
In this proposed process, self-aligned formation of metal connection is performed between the substrate and the semiconductor chip by melting metal filler (i.e., electrically conductive particles) contained in the resin. However, according to “10th Symposium on “Microjoining and Assembly Technology in Electronics” Feb. 5-6, 2004, pp. 183-188” (which is hereinafter referred to also as “Non-patent literature 3”) and “9th Symposium on “Microjoining and Assembly Technology in Electronics” Feb. 6-7, 2003, pp. 115-120” (which is hereinafter referred to also as “Non-patent literature 4”), there is noting else that the mechanism of the self-aligned formation of the metal connection is studied.
Non-patent literatures 1, 2 and Patent literature 4 disclose that a reducing resin is used as the resin. This reducing resin is a so-called “no-flow type underfill material”. See Japanese Patent Kokai Publication No. 2001-329048 (which is hereinafter referred to also as “Patent literature 5”), for example. When acid anhydride serving as a curing agent is added to the reducing resin, the acid anhydride is hydrolyzed to give carboxylic acid, and thereby flux property is obtained.
Patent literature 4 describes that the electrically conductive particles are allowed to aggregate on electrodes due to dispersibility of the particles and wettability, and thereby the lowest content of the particles in the resin is preferably 20% by volume or more, more preferably 30% by volume or more.